Recently, nonvolatile memories that do not lose recorded data even when power is turned off, such as electronically erasable programmable read only memories which allow erasure of whole blocks at a time (Flash EEPROMs) and ferroelectric random access memories (FeRAMs), have been applied to more and more semiconductor memory devices.
In a nonvolatile memory and system using the nonvolatile memory, a memory section of the nonvolatile memory stores operation modes thereof and operation modes of the system for the purpose of optimization of the system. If the memory section is configured to perform redundancy replacement, defects occurring in the memory section used by the system, if any, are repaired using addresses for redundancy replacement held in the memory section.
Conventionally, in order to optimize operation modes of a memory section and operation modes of a system or to perform redundancy replacement, chip data containing the operation modes or an address for the redundancy replacement is stored in a region of a nonvolatile memory section beforehand, and the nonvolatile memory section is initialized by reading out the chip data from the region after power has been turned on, thereby initializing the operation modes of the nonvolatile memory section and of the system and setting redundancy replacement, for example.
Hereinafter, a known semiconductor memory device having a nonvolatile memory will be described with reference to the drawing.
FIG. 7 shows a circuit configuration of a known semiconductor memory device.
As shown in FIG. 7, the known semiconductor memory device includes a first memory cell block 101, a second memory cell block 102, a third memory cell block 103 and a fourth memory cell block 104, which are regions for storing user data (usually memory cells) arranged in columns and rows and each of which is made up of a plurality of nonvolatile memory cells.
The first memory cell block 101 is provided with a chip-data storing region 101b for storing chip data including operation modes of the memory cell block and an address for redundancy replacement, for example, as well as a normal memory cell 101a. 
The memory cell blocks 101 through 104 are connected to a memory control circuit 110, which receives an internal control signal from a command decoder 111 for decoding an external command from a microcomputer 120. The memory control circuit 110 is connected to a system register 112 for temporarily storing the operation modes and the address for redundancy replacement.
In initialization of the semiconductor memory device thus configured, the microcomputer 120 reads out the chip data from the chip-data storing region 101b via the memory control circuit 110 and writes the chip data into the system register 112 after power has been turned on, thereby setting the operation modes of the device and performing redundancy replacement, for example. In this case, to initialize the device normally, the chip-data storing region 101b needs to pass a memory test. If a failure is found at even one address in the chip-data storing region 101b, the whole of the semiconductor chip is considered a defective.
As described above, the known semiconductor memory device has a first problem that a failure occurring at an address in the chip-data storing region 101b makes the semiconductor chip considered as a detective even if the memory cell blocks 101 through 104 have no defect.
In addition, the known semiconductor memory device has a second problem that no measure has been taken to date against unstableness of the power source voltage which occurs because the device is initialized immediately after power has been turned on and which therefore requires highly reliable operation as compared to normal operation.
Further, input of the external command during the initialization might cause the setting of the system operation modes and address information for redundancy replacement to be lost. This is serious especially in memories such as FeRAMs that perform destructive read out (a third problem).